ECP5 Evaluation Board

Lattice Semiconductor ECP5 Evaluation Board is designed to allow users to investigate and experiment with the ECP5-5G Field Programmable Gate Array (FPGA) features. This evaluation board features 178 general-purpose I/Os, 20 differential pair I/Os, four 5G SERDES channels, onboard boot flash, and multiple reference clock sources. The various clock sources include 12MHz from the U1 FTDI chip, 200MHz from the X2 differential oscillator, and an X5 oscillator for the LVDS source sync clock.