The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down converters. In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control function in a communications receiver.