วงจรเฟสล็อกลูป (PLL) ใหม่ล่าสุด

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ตัวกรองที่ใช้งาน:

03/11/2568

- Devices have a high-frequency capability, low jitter, and programmable clock input and output delay.

01/02/2566

- Features high output frequency, ultra-low noise floor, and very low skew clocks distribution.

09/15/2565

- This JESD buffer, multiplexer, and divider have a high-frequency capability & extremely low jitter.

กำลังดู: 1 - 3 จาก 3

กรองตาม:

10/01/2568

- Suited for local oscillator generation for 5G applications or data converter clock applications.

03/11/2568

- Devices have a high-frequency capability, low jitter, and programmable clock input and output delay.

08/01/2567

- Ultra-low noise frequency synthesizers used to implement LOs as high as 10GHz.

07/24/2567

- A high-performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated VCO.

01/02/2566

- Features high output frequency, ultra-low noise floor, and very low skew clocks distribution.

09/15/2565

- This JESD buffer, multiplexer, and divider have a high-frequency capability & extremely low jitter.

กำลังดู: 1 - 6 จาก 6